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Kinetis SDK API Reference Manual
1.0.0-beta
Freescale Semiconductor, Inc.
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The section describes the programming interface of the DMA HAL driver. More...
Data Structures | |
| struct | dma_channel_link_config_t |
| Data structure for data structure configuration. More... | |
| union | dma_error_status_t |
| Data structure to get status of the DMA channel status. More... | |
Enumerations | |
| enum | dma_status_t { kStatus_DMA_Success = 0U, kStatus_DMA_InvalidArgument = 1U, kStatus_DMA_Fail = 2U } |
| DMA status. More... | |
| enum | dma_transfer_size_t { kDmaTransfersize32bits = 0x0U, kDmaTransfersize8bits = 0x1U, kDmaTransfersize16bits = 0x2U } |
| DMA transfer size type. More... | |
| enum | dma_modulo_t { kDmaModuloDisable = 0x0U, kDmaModulo16Bytes = 0x1U, kDmaModulo32Bytes = 0x2U, kDmaModulo64Bytes = 0x3U, kDmaModulo128Bytes = 0x4U, kDmaModulo256Bytes = 0x5U, kDmaModulo512Bytes = 0x6U, kDmaModulo1KBytes = 0x7U, kDmaModulo2KBytes = 0x8U, kDmaModulo4KBytes = 0x9U, kDmaModulo8KBytes = 0xaU, kDmaModulo16KBytes = 0xbU, kDmaModulo32KBytes = 0xcU, kDmaModulo64KBytes = 0xdU, kDmaModulo128KBytes = 0xeU, kDmaModulo256KBytes = 0xfU } |
| Configuration type for the DMA modulo. | |
| enum | dma_channel_link_type_t { kDmaChannelLinkDisable = 0x0U, kDmaChannelLinkChan1AndChan2 = 0x1U, kDmaChannelLinkChan1 = 0x2U, kDmaChannelLinkChan1AfterBCR0 = 0x3 } |
| DMA channel link type. More... | |
DMA HAL channel configuration | |
| static void | dma_hal_configure_source_address (uint32_t instance, uint32_t channel, uint32_t address) |
| Configures the source address. More... | |
| static void | dma_hal_configure_dest_address (uint32_t instance, uint32_t channel, uint32_t address) |
| Configures the source address. More... | |
| static void | dma_hal_configure_count (uint32_t instance, uint32_t channel, uint32_t count) |
| Configures the bytes to be transferred. More... | |
| static uint32_t | dma_hal_get_unfinished_bytes (uint32_t instance, uint32_t channel) |
| Gets the left bytes not to be transferred. More... | |
| static void | dma_hal_enable_interrupt (uint32_t instance, uint8_t channel) |
| Enables the interrupt for the DMA channel after the work is done. More... | |
| static void | dma_hal_disable_interrupt (uint32_t instance, uint8_t channel) |
| Disables the interrupt for the DMA channel after the work is done. More... | |
| static void | dma_hal_set_cycle_steal (uint32_t instance, uint8_t channel, bool isCycleSteal) |
| Configure the DMA transfer mode to cycle steal or continuous modes. More... | |
| static void | dma_hal_set_autoalign_ability (uint32_t instance, uint8_t channel, bool isEnabled) |
| Configures the auto-align feature. More... | |
| static void | dma_hal_set_async_dma_request_ability (uint32_t instance, uint8_t channel, bool isEnabled) |
| Configures the a-sync DMA request feature. More... | |
| static void | dma_hal_set_source_increment (uint32_t instance, uint32_t channel, bool isEnabled) |
| Enables/Disables the source increment. More... | |
| static void | dma_hal_set_dest_increment (uint32_t instance, uint32_t channel, bool isEnabled) |
| Enables/Disables destination increment. More... | |
| static void | dma_hal_configure_source_transfersize (uint32_t instance, uint32_t channel, dma_transfer_size_t transfersize) |
| Configures the source transfer size. More... | |
| static void | dma_hal_configure_dest_transfersize (uint32_t instance, uint32_t channel, dma_transfer_size_t transfersize) |
| Configures the destination transfer size. More... | |
| static void | dma_hal_trigger_start (uint32_t instance, uint32_t channel) |
| Triggers the start. More... | |
| static void | dma_hal_configure_source_modulo (uint32_t instance, uint32_t channel, dma_modulo_t modulo) |
| Configures the modulo for source address. More... | |
| static void | dma_hal_configure_dest_modulo (uint32_t instance, uint32_t channel, dma_modulo_t modulo) |
| Configures the modulo for destination address. More... | |
| static void | dma_hal_set_dma_request (uint32_t instance, uint32_t channel, bool isEnabled) |
| Enables/Disables the DMA request. More... | |
| static void | dma_hal_set_disable_dma_request_after_done (uint32_t instance, uint32_t channel, bool isDisabled) |
| Configures the DMA request state after the work is done. More... | |
| void | dma_hal_set_channel_link (uint32_t instance, uint8_t channel, dma_channel_link_config_t *mode) |
| Configures the channel link feature. More... | |
| static void | dma_hal_clear_status (uint32_t instance, uint8_t channel) |
| Clears the status of DMA channel. More... | |
| static dma_error_status_t | dma_hal_get_status (uint32_t instance, uint8_t channel) |
| Gets the DMA controller channel status. More... | |
| struct dma_channel_link_config_t |
Data Fields | |
| dma_channel_link_type_t | linkType |
| Channel link type. | |
| uint32_t | channel1 |
| Channel 1 configuration. | |
| uint32_t | channel2 |
| Channel 2 configuration. | |
| union dma_error_status_t |
Data Fields | |
| struct { | |
| uint32_t dmaBytesToBeTransffered: 24 | |
| Bytes to be transferred. | |
| uint32_t dmaTransDone: 1 | |
| DMA channel transfer is done. More... | |
| uint32_t dmaBusy: 1 | |
| DMA is running. More... | |
| uint32_t dmaPendingRequest: 1 | |
| A transfer remains. More... | |
| uint32_t _reserved1: 1 | |
| uint32_t dmaDestBusError: 1 | |
| Bus error on destination address. | |
| uint32_t dmaSourceBusError: 1 | |
| Bus error on source address. | |
| uint32_t dmaConfigError: 1 | |
| Configuration error. | |
| uint32_t _reserved0: 1 | |
| } | u |
| uint32_t | b |
| uint32_t dma_error_status_t::dmaTransDone |
| uint32_t dma_error_status_t::dmaBusy |
| uint32_t dma_error_status_t::dmaPendingRequest |
| enum dma_status_t |
| enum dma_transfer_size_t |
|
inlinestatic |
Each SAR contains the byte address used by the DMA to read data. The SARn is typically aligned on a 0-modulo-size boundary-that is on the natural alignment of the source data. Bits 31-20 of this register must be written with one of the only four allowed values. Each of these allowed values corresponds to a valid region of the devices' memory map. The allowed values are: 0x000x_xxxx 0x1FFx_xxxx 0x200x_xxxx 0x400x_xxxx After they are written with one of the allowed values, bits 31-20 read back as the written value. After they are written with any other value, bits 31-20 read back as an indeterminate value.
This function enables the request for a specified channel.
| instance | DMA instance. |
| channel | DMA channel. |
| address | memory address pointing to the source address. |
|
inlinestatic |
Each DAR contains the byte address used by the DMA to read data. The DARn is typically aligned on a 0-modulo-size boundary-that is on the natural alignment of the source data. Bits 31-20 of this register must be written with one of the only four allowed values. Each of these allowed values corresponds to a valid region of the devices' memory map. The allowed values are: 0x000x_xxxx 0x1FFx_xxxx 0x200x_xxxx 0x400x_xxxx After they are written with one of the allowed values, bits 31-20 read back as the written value. After they are written with any other value, bits 31-20 read back as an indeterminate value.
This function enables the request for specified channel.
| instance | DMA instance. |
| channel | DMA channel. |
|
inlinestatic |
Transfer bytes must be written with a value equal to or less than 0F_FFFFh. After being written with a value in this range, bits 23-20 of the BCR read back as 1110b. A write to the BCR with a value greater than 0F_FFFFh causes a configuration error when the channel starts to execute. After they are written with a value in this range, bits 23-20 of BCR read back as 1111b.
| instance | DMA instance. |
| channel | DMA channel. |
| count | bytes to be transferred. |
|
inlinestatic |
| instance | DMA instance. |
| channel | DMA channel. |
|
inlinestatic |
This function enables the request for specified channel.
| instance | DMA instance. |
| channel | DMA channel. |
|
inlinestatic |
This function disables the request for a specified channel.
| instance | DMA instance. |
| channel | DMA channel. |
|
inlinestatic |
If continuous mode is enabled, DMA continuously makes write/read transfers until BCR decrement to 0. If continuous mode is disabled, DMA write/read is only triggered on every request. s
| instance | DMA instance. |
| channel | DMA channel. |
| isContinue | 0 means cycle-steal mode, 1 means continuous mode. |
|
inlinestatic |
If auto-align is enabled, the appropriate address register increments, regardless of whether it is a source increment or a destination increment.
| instance | DMA instance. |
| channel | DMA channel. |
| isEnable | 0 means disable auto-align. 1 means enable auto-align. |
|
inlinestatic |
Enables/Disables the a-synchronization mode in a STOP mode for each DMA channel.
| instance | DMA instance. |
| channel | DMA channel. |
| isEnable | 0 means disable DMA request a-sync. 1 means enable DMA request -. |
|
inlinestatic |
Controls whether the source address increments after each successful transfer. If enabled, the SAR increments by 1,2,4 as determined by the transfer size.
| instance | DMA instance. |
| channel | DMA channel. |
| isEnabled | Enabled/Disable increment. |
|
inlinestatic |
Controls whether the destination address increments after each successful transfer. If enabled, the DAR increments by 1,2,4 as determined by the transfer size.
| instance | DMA instance. |
| channel | DMA channel. |
| isEnabled | Enabled/Disable increment. |
|
inlinestatic |
| instance | DMA instance. |
| channel | DMA channel. |
| transfersize | enum type for transfer size. |
|
inlinestatic |
| instance | DMA instance. |
| channel | DMA channel. |
| transfersize | enum type for transfer size. |
|
inlinestatic |
When the DMA begins the transfer, the START bit is cleared automatically after one module clock and always reads as logic 0.
| instance | DMA instance. |
| channel | DMA channel. |
|
inlinestatic |
| instance | DMA instance. |
| channel | DMA channel. |
| modulo | enum data type for source modulo. |
|
inlinestatic |
| instance | DMA instance. |
| channel | DMA channel. |
| modulo | enum data type for dest modulo. |
|
inlinestatic |
| instance | DMA instance. |
| channel | DMA channel. |
| isEnabled |
|
inlinestatic |
Disables/Enables the DMA request after a DMA DONE is generated. If it works in the loop mode, this bit should not be set.
| channel | DMA channel. |
| isDisabled | 0 means DMA request would not be disabled after work done. 1 means disable. |
| void dma_hal_set_channel_link | ( | uint32_t | instance, |
| uint8_t | channel, | ||
| dma_channel_link_config_t * | mode | ||
| ) |
| channel | DMA channel. |
| mode | Mode of channel link in DMA. |
|
inlinestatic |
This function clears all status for specified DMA channel. The error status and DONE status would all be cleared.
| channel | DMA channel. |
|
inlinestatic |
Gets the status of the DMA channel. The user can get the error status, as to whether the descriptor is finished or there are bytes left.
| channel | DMA channel. |
| mode | Mode of channel link in DMA. |